This invention relates to a process for manufacturing a dynamic random access memory (DRAM) cell, and more particularly to such a process for manufacturing a DRAM cell wherein each DRAM cell is formed of a single transistor and a single capacitive storage device, and has a high capacitance.
In a large-scale integrated DRAM, a memory cell having a combination of a single transistor coupled with a single capacitive device has been widely used, and the combination is referred to as a "single transistor cell" for which a folded bit line array is employed as illustrated in FIG. 1 showing a schematic circuit diagram of a single transistor DRAM cell array. Referring to the FIG. 1, a transistor Q is a NMOS transistor, a bit line B is connected to a drain D of the transistor, a word line W is connected to a gate G of the transistor, a source of the transistor is connected to a storage capacitor C, and the other side of the capacitor is coupled to a silicon substrate.
Referring to FIG. 2, a plan view showing the layout according to the circuit configuration of FIG. 1, the word line W represents a second polysilicon strip 50, the bit line B represents a metal strip 52 formed of aluminium and so on, a region 54 is a first polysilicon region for a storage capacitor and a region 60 is a N+ source region formed by an ion implantation of N-type impurities, said source region connecting with a conductive layer under the first polysilicon region 54 by way of a conductive layer below a mini-field oxide region 58. A region 62 is a drain region formed by an ion implantation of N-type impurities, a region 56 is a gate region wherein a gate oxide is formed under the second polysilicon region and a portion under the oxide becomes a channel layer, and a window 64 is a metal-silicon connecting part for coupling the drain 62 and the bit line 52. In prior art, the mini-field oxide layer 58 is formed at the same time that a surface insulating layer of the first polysilicon region 54 overlapped in the upper part of the capacitive region is formed, and arsenic (As) of an arsenic ion implantation layer in a silicon substrate surface below the storage capacitor region, which becomes an electrode of the storage capacitor, is diffused through a side diffusion into a silicon substrate surface below the mini-field oxide layer. By using these facts, a method of the prior art has been widely employed in which said source of the transistor and said arsenic ion implantation layer are coupled to each other.
In making use of this processing method as mentioned above, when forming a mini-field oxide layer, the arsenic ion-implanted in the silicon substrate surface often fails to be diffused enough into the connecting part of the mini-field oxide layer and the source region of the transistor due to its low diffusion factor. Also, a decrease in the arsenic ion density arising from an out diffusion results in a high resistance between the capacitor and the transistor. Thus due to said decrease, a margin of supply voltage to a DRAM is reduced and refresh time is rapidly decreased, thereby resulting in an inability to perform a high-speed operation. Moreover, in the worst case, an open circuit in the connection between said capacitor and transistor often makes the manufacture of an entire chip a failure.
Another problem is that there is increased possibility of a soft-error occurrence, wherein data "1" stored in the capacitor is changed into data "0" because the amount of electric charge is reduced in a storage region of minority carriers resulting from .alpha.(Alpha) particles which are generated from uranium-group substances of fabrication materials of memory chips, as a cell area and an electric charging amount stored in a cell are both reduced accommodate the density of to a large intergrated circuit of semiconductor memory devices. Another problem in the prior art is that there is also an increased a possibility of a soft-error occurrence by which the data "0" reads out to be the data "1", because, as the minority carriers generated by the .alpha. particle move to the N+ drain region of a transistor, the electric potential in a bit line goes down.